Electrically erasable and programmable read-only memory (EEPROMs) are non-volatile memory devices which are programmed and erased using electrical signals. An EEPROM finds application in data processing systems when it is necessary to preserve changes made to memory during operation of the data processing system. In these situations the EEPROM maintains the state of the memory throughout a power down of the system.
An erasable non-volatile memory device typically contains many memory cells. A memory cell is a portion of the memory which holds one unit, or bit, of data. Typically, a memory cell includes at least one transistor or storage device. Memory cells are organized into groups, where a typical grouping is called a byte and includes eight bits of data. Each group or byte may then be individually programmed. Each byte is identified by its position in the memory array, where each byte has a unique combination of wordline and bitline locations. The wordline and bitline information forms an effective address of the byte of memory, similar to the identification of entries in a mathematical array by row and column identification. Erasing is provided either for the entire memory array in bulk, for an individual wordline, for a group of wordlines, for an individual byte or for a group of bytes.
Identification of the wordline and bitline of a specific memory cell is typically provided by a wordline control and a bitline control. A typical EEPROM cell includes a floating gate transistor which is coupled to the wordline control and a select transistor which is coupled to the bitline control. The floating gate transistors store the digital value associated with the memory cell. For programming or erasing, the wordline control provides sufficient voltage to the floating gate transistor to allow programming or erasing. The select transistors select an individual EEPROM cell in the indicated wordline to be erased or programmed.
According to one known erasing scheme of an EEPROM, the control associated with a given wordline is biased at a high positive voltage, such as 12 to 15 volts, while the bitlines are held at a lower reference potential, thus erasing the entire wordline, i.e. changing the charge stored on each floating gate transistor coupled to the control line to an erased state. It is noted that as described herein, a memory cell is defined as erased when the floating gate device is in its non-conductive state, corresponding to a logical "0," and a memory cell is defined as programmed when the floating gate device is in its conductive state, corresponding to a logical "1." Note that alternate embodiments may define the memory cell using opposite polarity. During an erase operation, the voltages are maintained on the control and select lines for a time period sufficient to allow erasing of each cell. It is therefore desirable to erase multiple cells concurrently and thus realize a reduction in total erase time. Certain EEPROM cells have separate select transistor, wherein the select gates are typically turned on during the erase operation, however this is not essential. At completion of the erase operation, the floating gate devices are charged to a threshold voltage which is sufficient to prevent conduction during a read operation. Any number of control lines may be biased simultaneously, allowing block and bulk erase. For block erase multiple rows in the memory array are erased at one time. For a bulk erase all rows are erased at the same time. Block and bulk erasing reduce the total time required to erase the memory array, as multiple cells are erased concurrently.
According to a known EEPROM programming scheme the control line is biased to a high negative voltage, such as -12 to -15 volts and the floating gate device is programmed to a conductive state. During the programming operation the associated bitline is then biased to a moderately high positive voltage with respect to the control line, such as 5 volts. A given row has a plurality of bitlines each corresponding to a bit in the row. Since the control line runs through multiple bits in a given row, it is desirable to isolate those bits that are to remain in an erased state and prevent programming. This is done by applying a bias voltage to the bitlines associated with bits that are not to be programmed. The biasing voltage is at ground or a low reference voltage level. Similarly, control lines for unselected rows are isolated by applying a bias voltage of about 3.5 volts. Biasing the unselected control lines minimizes any bitline disturbance or any band-to-band tunneling effects. Note that during programming, often neighboring bits are effected by the voltages used to program desired bits. This is true as neighboring bits are exposed to the same high voltages during programming.
One particular configuration of EEPROM is a flash EEPROM. Flash EEPROMs provide electrical erasing and programming capability and generally have an increased circuit density. This increased circuit density typically comes at the cost of only being able to block erase a flash EEPROM array. Typically, the array is erased in a single step or a "flash", and thus the term flash EEPROM. As circuit design dimensions continue to decrease, there is a need to maintain programming and erase voltages for these types of memories, without increasing the silicon area required to create and maintain these voltages. Typically, n-channel devices maintain a V.sub.threshold value which increases as the source terminal voltage of the transistor increases. For typically high erase and programming voltages, the n-channel threshold voltage introduces too great of a loss for efficient operation. This often requires additional circuitry to maintain the voltage necessary to write to the memory cells. The additional circuitry often is large relative to the size of the memory array.
There is a need for a method of writing to non-volatile erasable memories which does not introduce the disturbance effects on neighboring memory cells as mentioned above (and as further explained below). Additionally, it is desirable that a method of writing to a memory is able to isolate individual bits within the memory array. Particularly in memories which have a very high number of write cycles, for example, greater than 100 k write cycles, it is desirable to have a select device which effectively protects transistors sharing a common bitline during programming of other rows in the memory array.
Another desirable feature of a memory array is long data retention. Data retention refers to the time in which the memory cells hold their last written state (e.g. how long a programmed cell maintains its logical "1" state and how long an erased cell maintains its logical "0" state). Over time electron leakage occurs in the cells and if enough charge is lost a previously programmed cell will be read as an erased celll even though the cell has not intentionally been re-written. This is a serious problem in applications requiring a high level of data integrity. Traditional EEPROM approaches to ensure data integrity have been to periodically read the data from EEPROM, to store the read data in random access memory (RAM), to erase the entire EEPROM array, and then to re-program the array with the same data values as stored in RAM. Although effective at refreshing the data in an EEPROM array, this approach has a drawback for high security applications, such as integrated circuits used in smartcards. The drawback is that in the refresh cycle, the EEPROM data is read and then stored in RAM, causing the data to circulated on an data bus of the integrated circuit. Having the data, and especially the data of the entire array, on the bus provides an opportunity for a hacker to be able to "catch" the data during the refresh sequence, and therefore is not a desirable solution to the data retention problem in high security applications.